Industry experience:

• 2000-2021 – Motorola Inc. -> Freescale -> NXP --- Senior Principal R&D Engineer, Phoenix, AZ
  • Highlights:
    • Lead: Defining design strategies, implementations, floor plans, integration (chip-level and chip/package/pcb) and conducting simulation, characterization, analysis, qualification, CQI, in term of signal isolation/interference for products and design teams across the company
      • Products:
        • RF: Car-to-Car communication, Automotive Radar, Car Radio, Cellphone, Zigbee, Bluetooth, Medical, etc.
        • Buck-converter/CAN/LIN integration
        • Microcontrollers
    • Product modeling, support, verification, qualification and debug for EMC/on-chip emissions compliance, EFT, latch-up and parasitic BJT
    • Develop, evaluate, qualify infrastructure for modeling and simulation applicable to aforementioned activities and products, from technology/TCAD/PDK, to design rules and best practices, to methodology, design flows, and tools
    • Develop methodologies and niche internal tools
      • For signal isolation/interference
        • Placement and sizing of on-chip decoupling capacitors, power grid design, and power delivery
        • Integrated Circuit Emissions Modeling (ICEM)
        • Chip-package-pcb co-design
      • For prediction and prevention of small and large signal parasitic bipolar effects
        • Locate, characterize, model, and report risky parasitic bipolars (NPNs, PNPs, SCRs) in a GDS design database
      • Circuit design using reconfigurable and adaptive architectures (analog, low-voltage, high noise immunity)
    • Latch-up and parasitic bipolar predictive analysis and verification of products across company, as well as post-failure debug analysis
    • Provide training and guidance for design teams in signal integrity and latch-up fundamentals and techniques for design, prevention, and optimizations
    • Research coordinator of six summer internships
• 1996-2000 – Xerox Corporation and Kodak Corporation – Rochester N.Y.
  • Year-round intern funding my Ph.D., working on design, test, and evaluation of noise isolation and signal integrity aspects for inkjet printer circuits and imaging sensors/circuits
• 1990-1995 – Baneasa S.A. Semiconductors --- Analog design engineer, Bucharest, Romania
  • Analog circuit design for consumer products, primarily bipolar, including op-amps, audio amplifiers, ADC/DAC converters. Prototype sample characterization and qualification, product data sheet and product standard development, customer design reviews
• 1994-1995 – Research Institute for Electronic Components (ICCE) – Associate R&D Engineer, Bucharest, Romania

Academic experience:

• 2002-present – Arizona State University (ASU) --- EEE Adjunct Professor, Tempe, AZ
  • Taught more than 25 class sessions (more than 1,000 students)
    • Mostly graduate level classes, such as Digital VLSI Design
    • Undergraduate level classes as well, such as Analog Circuit Design

Detailed List of Publications

1. M. Grau Novellas, R. Serra, M. Rose and R. Secareanu, "On-Chip Interference Generation Mechanisms From an Electromagnetic Perspective," IEEE Transactions on Electromagnetic Compatibility, vol. 60, no. 6, pp. 1889-1897, Dec. 2018
2. M. G. Novellas, R. Serra, M. Rose and R. Secareanu, "Efficient Modeling of Multistage Integrated Circuit Passive Isolation Structures," IEEE Transactions on Electromagnetic Compatibility, vol. 60, no. 2, pp. 544-547, April 2018
3. R. Secareanu, C. Johnson and M. Stockinger, "An automated tool for minimizing product failures due to parasitic BJTs and SCRs," Proceedings of IEEE Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), pp. 1-7, Sept. 2017
4. M. Stockinger and R. Secareanu, "Unexpected Latch-Up Through CMOS Triple-Well Structures," IEEE Transactions on Device and Materials Reliability, vol. 15, no. 3, pp. 272-279, Sept. 2015
5. M. Stockinger, R.M. Secareanu, and O. Hartin, "Device Interactions Between ESD Diodes and NMOS Clamps in CMOS Processes", Proceedings of IEEE Electrical Overstress/Electrostatic Discharge Symposium, pp. 1-9, May 2014
6. S. Kose, R.M. Secareanu, E.G. Friedman and O. Hartin, "Current Profile of a Microcontroller to Determine Electromagnetic Emissions", Proceedings of IEEE International Symposium on Circuits and Systems, pp. 2650-2653, May 2013
7. R.M. Secareanu, O. Hartin, J. Feddeler, R. Moseley, J. Shepherd, B. Vrignon, J. Yang, Q. Li, H. Zhao, W. Li, W. Linpeng, E. Salman, R. Wang, D. Blomberg, P. Parris, "Impact of Low-Doped Substrate Areas on the Reliability of Circuits Subject to EFT Events", Proceedings of the IEEE System-on-a-Chip Conference, pp. 21-24, September 2010
8. R. Jakushokas, R.M. Secareanu, E. Salman, C. Recker, E.G. Friedman and O. Hartin, "Compact Substrate Models for Efficient Noise Coupling and Signal Isolation Analysis", Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2346-2349, May 2010
9. R.M. Secareanu, J. Yang, Q. Li, L. Briones, S. Eid, V. Jean-Stephane and O. Hartin, "Impact of Module Design on the Signal Isolation of Mixed-Signal RF Applications", Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 3749-3752, May 2010
10. E. Salman, R.M. Secareanu, E.G. Friedman and O. Hartin, "Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 17, Issue 10, pp. 1559-1564, Oct. 2009
11. E. Salman, R.M. Secareanu, R. Jakushokas, E.G. Friedman and O. Hartin, "Methodology for Efficient Substrate Noise Analysis on Large-Scale Mixed-Signal Circuits". IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 17, Issue 10, pp. 1405-1418, Oct. 2009
12. E. Salman, R.M. Secareanu, E.G. Friedman and O. Hartin, "Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance", IEEE Transactions on Circuits and Systems I, Volume 56, Issue 5, pp. 997-1004, May 2009
13. M. Popovich, R.M. Secareanu, E.G. Friedman and O. Hartin, "Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale IC’s", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 16, Issue 12, pp. 1717-1721, Dec. 2008
14. E. Salman, R.M. Secareanu, E.G. Friedman and O. Hartin, "Equivalent Rise Time for Resonance in Power/Ground Noise Estimation", Proceeding of the IEEE International Symposium on Circuits and Systems, pp. 2422-2425, May 2008
15. E. Salman, R.M. Secareanu, R. Jakushokas, E.G. Friedman and O. Hartin, "Input Port Reduction for Efficient Substrate Extraction in Large Scale IC’s", Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 376-379, May 2008
16. E. Salman, R.M. Secareanu, E.G. Friedman and O. Hartin, "Dominant Substrate Noise Coupling Mechanism for Multiple Switching Gates", Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 261-266, March 2008
17. M. Popovich, R.M. Secareanu, E.G. Friedman, R.M and O. Hartin, "Efficient Placement of Distributed On-Chip Decoupling Capacitors in Nanoscale IC’s", Proceedings of the IEEE International Conference on Computer Aided Design, pp. 811-816, November 2007
18. R.M. Secareanu and A. Marshall, "System-on-Chip Integration – Challenges and Implications", Guest Editorial, Special Section, IEEE Transactions on VLSI Systems, Vol.15, No.10, pp. 1065-1066, October 2007
19. E. Salman, R. M. Secareanu, O. Hartin, and E.G. Friednman, "Substrate Noise Reduction Based on Noise-Aware Cell Design", Proceedings of the IEEE International System-on-a-Chip Conference on Circuits and Systems, pp. 3237-3230, May 2007
20. V. Kursun and E.G. Friedman, "Multi-Voltage CMOS Circuit Design", Wiley, October 2006, contributions
21. E. Salman, R.M. Secareanu and E.G. Friedman, "Substrate and Ground Interactions in Mixed-Signal Circuits",Proceedings of the IEEE International System-on-a-Chip Conference, pp. 293-296, Sept. 2006
22. R.M. Secareanu and O. Hartin, "Low-Power Architectures Using Localized Non-Volatile Memory and Selective Power Shut-Down", Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 377-380, May 2006
23. M. Popovich, R.M. Secareanu, M. Sotman, A. Kolodny and E.G. Friedman, "Maximum Effective Distance of On-Chip Decoupling Capacitors in Power Distribution Grids", Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 173-179, May 2006
24. M. Popovich, R.M. Secareanu, E.G. Friedman, and O. Hartin, "On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits", Proceedingsof the IEEE International System-on-a-Chip Conference", pp. 309-312, Sept. 2005
25. R.M. Secareanu, S.K. Banerjee, E. Nabity, A. Duvallet and O. Hartin, "Accurate Simulation Environment for Signal Isolation in Mixed-Signal Design", Proceedings of the IEEE System-on-a-Chip Conference, pp. 105-108, Sept. 2005
26. R.M. Secareanu, S.K. Banerjee, O. Hartin, V. Fernandez and E.G. Friedman, "Managing Substrate and Interconnect Noise from High Performance Repeater Insertion in a Mixed-Signal Environment", Proceedings of the IEEE International Symposium on Circuits and Systems, Vol.1, pp. 612-615, May 2005
27. R.M. Secareanu, Q. Li, S. Bharatan, C. Kyono, R. Thoma, M. Miller and O. Hartin, "Signal Integrity Implications of Inductor-to-Circuit Proximity", "Proceedings of IEEE International SOC Conference, pp. 69-72, September 2004
28. R.M. Secareanu and W. Peterson, "An Adaptive Circuits Concept to Address Mismatch in Analog Circuits", Proceedings of the IEEE International Symposium on Circuits and Systems",Vol.1, pp. 885-888, May 2004
29. R.M. Secareanu, S. Warner, S. Seabridge, C. Burke, J. Becerra, T.E. Watrobski, C. Morton, W. Staub, T. Teller, I.S. Kourtev and E.G. Friedman, "Substrate Coupling in Digital Circuits in Mixed-Signal Smart-Power Systems", IEEE Transactions on VLSI Systems, Vol.12, No.1, pp. 67-78, January 2004
30. R.M. Secareanu and P. Maniar, "Aspects and Implications of System-on-a-Chip Communication Circuits on Future Devuce and Nanotechnology Development", Proceedings of IEEE ASIC-SOC Conference, pp. 403-407, September 2003
31. R.M. Secareanu, F.K. Roy, S.S. Sapatnekar and Y.I Ismail, "High Performance Design Techniques in Nanometer Integrated Circuits", IEEE International Symposium on Circuits and Systems, Tutorial Guide, Vol.1, pp. 5-210, May 2003
32. R.M. Secareanu and D.H. Hartman, "A Low Voltage Low Noise CMOS Digital Family", Proceedings of IEEE ASIC-SOC Conference, pp. 198-202, September 2002
33. R.M. Secareanu and P. Maniar, "The Impact of Device Leakage on Digital Circuits", Proceedings of IEEE International Symposium on Circuits and Systems, Vol.2, pp. 7800-783, May 2002
34. R.M. Secareanu, W. Peterson, and D.H. Hartman, "A Low-Voltage Low-Noise Digital Buffer System", Proceedings of IEEE International Symposium on Circuits and Systems, Vol.4, pp. 181-184, May 2002
35. V. Kursun, R.M. Secareanu, and E.G. Friedman, "CMOS Voltage Interface Circuit for Low-Power Systems", Proceedings of IEEE International Symposium on Circuits and Systems, Vol.3, pp. 667-670, May 2002
36. R.M. Secareanu, M. Jones, M. Sadd, B. White and P. Maniar, "Circuit Challenges and Proposed Solutions Targeting Nanometer Technologies", Proceedings of the IEEE ASIC SOC Conference, pp. 325-329, September 2001
37. R.M. Secareanu, D. Albonesi, and E.G. Friedman, "A Dynamic Reconfigurable Clock Generator", Proceedings of the IEEE ASIC SOC Conference, pp. 330-334, September 2001
38. R.M. Secareanu, S. Warner, S. Seabridge, C. Burke, T.E. Watrobski, C. Morton, W. Staub, T. Teller and E.G. Friedman, "A Comparative Study of the Behavior of NMOS and CMOS Digital Circuits under Substrate Noise", Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 181-184, September 2001
39. R.M. Secareanu, S. Warner, S. Seabridge, C. Burke, T.E. Watrobski, C. Morton, W. Staub, T. Teller and E.G. Friedman, "Placement of Substrate Contacts to Minimize Substrate Noise in Mixed-Signal Integrated Circuits", Analog Integrated Circuits and Signal Processing Journal, Vol.28, No.3, pp. 253-264, September 2001
40. R.M. Secareanu and E.G. Friedman, "Applying Analog Techniques in Digital CMOS Buffers to Improve Speed and Noise Immunity", Analog Integrated Circuits and Signal Processing Journal, Vol.27, No.3, pp. 275-279, June 2001
41. R.M. Secareanu and E.G. Friedman, "A Differential High-Speed Digital CMOS Buffer with Hysteresis for Improved Noise Immunity", Proceedings of the IEEE ASIC SOC Conference, pp. 326-329, September 2000
42. R.M. Secareanu, S. Warner, S. Seabridge, C. Burke, T.E. Watrobski, C. Morton, W. Staub, T. Teller and E.G. Friedman, "Placement of Substrate Contacts to Alleviate Substrate Noise in Epi and Non-Epi Technologies", Proceedings of the IEEE 43rd Midwest Symposium on Circuits and Systems, pp. 1314-1318, August 2000
43. R.M. Secareanu and E.G. Friedman, "Low Power Digital CMOS Buffer System for Driving Highly Capacitive Interconnect Lines", Proceedings of the IEEE 43rd Midwest Symposium on Circuits and Systems, pp. 362-365, August 2000
44. R.M. Secareanu, S. Warner, S. Seabridge, C. Burke, T.E. Watrobski, C. Morton, W. Staub, T. Teller and E.G. Friedman, "Physical Design to Improve the Noise Immunity of Digital Circuits in a Mixed-Signal Smart-Power System", Proceedings of the IEEE International Symposium on Circuits and Systems, Vol.4, pp. 277-280, May 2000
45. R.M. Secareanu and E.G. Friedman, "Transparent Repeaters", Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 63-66, March 2000
46. R.M. Secareanu, S. Warner, S. Seabridge, C. Burke, T.E. Watrobski, C. Morton, W. Staub, T. Teller and E.G. Friedman, "Substrate Noise Distribution and Placement of Substrate Contacts to Alleviate Substrate Noise in Epi and Non-Epi Technologies", Proceedings of the IEEE 23rd Annual EDS/CAS Activities in Western New-York Conference, pp. 15-16, November 1999
47. R.M. Secareanu, V. Adler and E.G. Friedman, "Exploiting Hysteresis in a CMOS Buffer", Proceedings of the IEEE International Conference on Electronics, Circuits, and Systems, pp. 205-208, September 1999
48. R.M. Secareanu and E.G. Friedman, "A High Precision CMOS Current Mirror Divider", Proceedings of the IEEE International Symposium on Circuits and Systems, Vol.2, pp. 314-317, May 1999
49. R.M. Secareanu, J. Becerra, S. Warner and E.G. Friedman, "A Universal CMOS Voltage Interface Circuit", Proceedings of the IEEE International Symposium on Circuits and Systems, Vol.1, pp. 242-245, May 1999
50. R.M. Secareanu, I.S. Kourtev, J. Becerra, T.E. Watrobski, C. Morton, W. Staub, T. Teller and E.G. Friedman, "The Behavior of Digital Circuits under Substrate Noise in a Mixed-Signal Smart-Power Environment", Proceedings of the IEEE International Symposium on Power Semiconductor Devices and ICs, pp. 253-256, May 1999
51. R.M. Secareanu, I.S. Kourtev, J. Becerra, T.E. Watrobski, C. Morton, W. Staub, T. Teller and E.G. Friedman, "Noise Immunity of Digital Circuits in Mixed-Signal Smart-Power Systems", Proceedings of the IEEE Great Lakes Symposium on VLSI, pp. 314-317, February 1999
52. R.M. Secareanu and E.G. Friedman, "A High-Speed CMOS Buffer for Driving Large Capacitive Loads in Digital ASICs", Proceedings of the IEEE International ASIC Conference, pp. 365-368, September 1998
53. R.M. Secareanu and E.G. Friedman, "A CMOS Current Mirror/Divider for High Precision Applications", Proceedings of the IEEE 21st Annual EDS/CAS Activities on Western New York Conference, pp. 11, November 1997
54. R.M. Secareanu, S. Nan, M. Serbanescu, and P. Cazimirovitz, "Electrical Characterization of ZnO Based Varistors", Proceedings of the IEEE Romanian Annual International Semiconductor Conference, CAS-1994

Detailed List of Patents

• US Patents

1. Filed February 2022 - R.M. Secareanu, "Full-band Hi-Fi Audio Codec"
2. Filed February 2022 - R.M. Secareanu, "Binary Data Compression / Decompresion Method for Audio / Video and Data Communication and Storage"
3. Filed January 2022 - R.M. Secareanu, "Binary Encryption / Decryption Method for Secure Audio / Video Broadcast And Communication and for Data Transmission / Storage"
4. Filed August 2021 - R.M. Secareanu, "Binary Data Compression / Decopmpression Algorithm"
5. Filed April 2021 – R.M. Secareanu, "Isolated Pwell (IPW) with Improved Noise Isolation Efficiency at High Frequencies"
6. Filed March 2020 – R.M. Secareanu, M. Stockinger, "Improved Noise Isolation in an ESD Scheme"
7. US 201,900,81037 A1 – A. Bidzo, R.M. Secareanu, J. Klimczak, D. Clavin "RF ESD Inductor-based Cross-Domain Grounds ESD Protection for RF Applications"
8. US 10,615,252 – R.M. Secareanu, "Device Isolation"
9. US 10,580,856 – R.M. Secareanu, B. Grote, "Structure for Improved Noise Isolation"
10. US 8,957,496 – R.M. Secareanu, Q. Li, O. Hartin, S. Jalaleddine and M. Zunino, "Integrated Circuit Chip with Discontinuous Guard Ring"
11. US 7,834,428 – R.M. Secareanu, E. Salman and O. Hartin, "Apparatus and Method for Reducing Noise in Mixed-Signal Circuits and Digital Circuits"
12. US 7,683,483 – R.M. Secareanu, S.K. Banerjee, O. Hartin and S. Wipf – "Electronic Device with Connection Bumps"
13. US 7,608,913 and US 9,048,110 B2 – R.M. Secareanu, S.K. Banerjee and O. Hartin, "Noise Isolation Between Circuit Blocks in an Integrated Circuit Chip"
14. US 7,595,679 – M. Popovich, R.M. Secareanu, E.G. Friedman and O. Hartin, "Method and Aparatus to Reduce Noise Fluctuations in On-Chip Power Distribution Networks"
15. IPCOM000138959D – R.M. Secareanu, O. Hartin, W. Parmon and M. Popovich, "Design of a Distributed On-Chip Decoupling Capacitor Network – Correlation Between a Distributed Capacitor and Circuit Demands"
16. US 7,138,686 – R.M. Secareanu, E. Ferrer, S. Banerjee and O. Hartin, "Integrated Circuit with Improved Signal Noise Isolation and Method for Improving Signal Noise Isolation"
17. US 6,788,134 – R.M. Secareanu, "Low Voltage Current Sources/Current Mirrors"
18. IPCOM000012185D – R.M. Secareanu and M. Jones, "An Adaptive Circuits Concept"
19. US 6,366,127 – R.M. Secareanu and E.G. Friedman, "Digital CMOS Voltage Interface Circuits"
20. US 6,166,590 – R.M. Secareanu and E.G. Friedman, "Current Mirror and/or Divider Circuits with Dynamic Current Control which are Useful in Applications for Providing Series of Reference Currents, Subtraction, Summation and Comparison"
21. US 6,163,174 – R.M. Secareanu and E.G. Friedman, "Digital Buffer Circuits"

• International Patents

1. CN 101,432,881 B and TWI 427,762 and EP 198,9738 B1 and KR 101,342,877 B1 – R.M. Secareanu "Noise Isolation between Circuit Blocks in an Integrated Circuit Chip"
2. EP 345,7435 A1 and CN 109,509,748A – A. Bidzo, R.M. Secareanu - "Electrostatic Discharge Protection Structure"
3. IN2007DN07703A - R.M. Secareanu, E. Ferrer, S. Banerjee and O. Hartin, "Integrated Circuit with Improved Signal Noise Isolation and Method for Improving Signal Noise Isolation"

• Patent Applications into defensive or regular publications

1. R.M. Secareanu, J. Feddeler, M. Stockinger, O. Hartin, et al "Method to locate risky BJTs"
2. R.M. Secareanu, J. Feddeler, M. Stockinger, O. Hartin, et al "Method to instantly create a spice-compatible device model from an arbitrarily shaped three-dimensional parasitic BJT"
3. R.M. Secareanu, J. Feddeler, M. Stockinger, O. Hartin, et al "Method to form an SCR from arbitrarily shaped parasitic BJTs"
4. R.M. Secareanu, R. Jakushokas, C. Recker and O. Hartin "Signal Isolation Calculator"
5. R.M. Secareanu and O. Hartin, "An Efficient Triple-Well Scheme for Signal Isolation of Circuit Blocks in a Mixed-Signal System-on_chip"
6. R.M. Secareanu, E. Salman, O. Hartin, R. Jakushokas, and E.G. Friedman, "Method for Computationally Efficient Substrate Noise Analysis Based on Circuit Activity"
7. R.M. Secareanu, M. Popovich, E,G, Friedman, and O. Hartin, "Method to Reduce Noise Ripple on Power/Ground Lilnes by Using Distributed decoupling Capacitors"
8. R.M. Secareanu, S.K. Banerjee and O. Hartin, "Signal Isolation in Silicon-on-Insulator (SOI) Using patterned Implanted Ground Plane"
9. R.M. Secareanu and O. Hartin, "A Concept for Active Noise Cancelation of Substrate Noise"

IEEE & SRC Activities

• IEEE Member
• Member IEEE, Circuits and Systems Society, Past Member of IEEE Circuits and Systems Society Technical Committee on VLSI Systems and Applications
• Past Member of ASU Doctoral Supervisory Committee
• Past Member of the Motorola/Freescale Scientific and Technical Society
• Recipient of "SRC/GRC Mahboob Khan Outstanding Mentor Award" – 2007
• Recipient of "SRC/GRC Mentor Award" – 2007
• Tutorial presentation titled "Tools and Methodologies for Emission Prediction during the IC Design Flow", presented at "IEEE EMCcompo 2011", together with Bertrand Vrignon (Freescale Toulouse)
• Workshop presentation titled "Isolation Issues in Multi-Chip Radio Modules for Cellular Applications: On-Chip, Module-Chip, and Module" – part of the full day workshop titled "RF SOC Integration with Peripherals and the Demand for Attention to Coupling Effects in early Design Phases" – coauthor, presented at 2008 IEEE RFIC Symposium, June 2008
• Invited IEEE talk for the "Wireless and Devices IEEE Phoenix Section", titled "Signal Isolation – A Process, Device, or a Design Challenge?", May 2006
• Tutorial presentation at the "IEEE ISCAS 2003", titled "High-Performance Design Techniques in Nanometer Integrated Circuits", together with Kaushik Roy (Purdue), Sachin Sapatnekar (Minnesota), and Yehea Ismail (Northwestern)
• Tutorial presentation at the "IEEE SOCRT-2003" titled "Challenges for System-on-a-chip Integration", together with YrheaMassoud (Rice) and Khellah Muhammad (Intel)
• Tutorial presentation at the "IEEE ISCAS 2002", titled "Noise and Substrate Coupling in Communication Mixed-Signal ICs", part of the tutorial "RF and Mixed-Signal Circuits for Wireless Applications", together with Jose Epifanio da Franca (ChipIdea) and SayfeKiaei (ASU)
• Associate editor, Microelectronics Journal, 2013-2020
• Associate editor, Journal of Circuits, Systems, and Computers, 2007-2013
• Technical Program Co-Chair, 2011 IEEE-ASQED Organizing Committee Member
• Circuits and Systems Design Co-Chair, 2010 IEEE-ASQED
• Guest Editor, IEEE TVLSI, special section "System-on-Chip Integration", vol.15, No.10, Oct. 2007
• Publications Chair, 2006 IEEE-SOCC
• Associate Editor, IEEE-TVLSI, 2001-2005
• TPC Member, IEEE-ISCAS, IEEE-SIPS, IEEE-SOCC, IEEE-SOCRT, IEEE NASA/ESA, IEEE-ASQED
• Session-chair, Track-chair, reviewer, for multiple conferences and journals
• Contributed to proposal for an SRC Freescale- University of Rochester Research Customization project "Placement of on-chip decoupling capacitors" 2004-2007 SRC task
• Contributed to proposal "Clock Distribution Network Design Methodology for reduced Emissions" 2009-2010 project
• Contributed to SRC proposal "Design and Automation of a Novel Low-Swing Clocking Methodology with Reduced Delay Uncertainty", Freescale-Stony Brook 2013-2016 SRC task